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| (R) TS68HC901 HCMOS MULTI-FUNCTION PERIPHERAL The TS68HC901 CMFP (CMOS Multi-Function Peripheral) is a combination of many of the necessary peripheral functions in a microprocessor system. Included are : NPUT/OUTPUT PINS * Individually programmable direction * Individual interrupt source capability - Programmable edge selection NTERRUPT CONTROLLER * 8 Internal sources * 8 External sources * Individual source enable * Individual source masking * Programmable interrupt service modes - Polling - Vector generation - Optional In-service status * Daisy chaining capability MERS WITH INDIVIDUALLY PROGRAMMABLE PRESCALING * Two multimode timers - Delay mode - Pulse width measurement mode - Event counter mode * Two delay mode timers * Independent clock input * Time out output option NGLE CHANNEL USART * Full Duplex * Asynchronous to 65 kbps * Byte synchronous to 1 Mbps * Internal/External baud rate generation * DMA handshake signals * Modem control * Loop back mode BLE .8I .16SOURCEI .FOURTI .SI 48 PDIP48 1 PLCC52 (Ordering Information at the end of the Datasheet .68000BUSCOMPATI DESCRIPTION The use of the CMFP in a system can significantly reduce chip count, thereby reducing system cost. The CMFP is completely 68000 bus compatible, and 24 directly addressable internal registers provide the necessary control and status interface to the programmer. The CMFP is a derivative of the MK3801 STI, a Z80 family peripheral. 1/42 September 1992 TS68HC901 INTRODUCTION The TS68HC901 multi-function peripheral (CMFP) is a member of the 68000 peripherals. The CMFP directly interfaces to the 68000 processor via an asynchronous bus structure. Both vectored and polled interrupt schemes are supported, with the CMFP providing unique vector number generation for each of its 16 interrupt sources. Additionally, handshake lines are provided to facilitate DMAC interfacing. Refer to block diagram of the TS68HC901. The TS68HC901 performs many of the functions common to most microprocessor-based systems. The resources available to the user include: ght Individually Programmable I/O Pins with Interrupt Capability Source Interrupt Controller with Individual Source Enabling and Masking Timers, Two of which are Multi-Mode Timers Figure 1: TS68HC901 Block Diagram .Ti .Si .Ei .16.Four mers may be used as Baud Rate Generators for the Serial Channel ngle-Channel Full-Duplex Universal Synchronous / Asynchronous Receiver-Transmitter (USART) that Supports Asynchronous and with the Addition of a Polynomial Generator Checker Supports Byte Synchronous Formats By incorporating multiple functions within the CMFP, the system designer retains flexibility while minimizing device count. From a programmer's point of view, the versatility of the CMFP may be attributed to its register set. The registers are well organized and allow the CMFP to be easily tailored to a variety of applications. All of the 24 registers are also directly addressable which simplifies programming. The register map is shown in Figure 2. 2/42 (R) TS68HC901 Figure 2 : CMFP Register Map. Address Binary Hex RS5 01 03 05 07 09 0B 0D 0F 11 13 15 17 19 1B 1D 1F 21 23 25 27 29 2B 2D 2F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 RS3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 GPIP AER DDR IERA IERB IPRA IPRB ISRA ISRB IMRA IMRB VR TACR TBCR TCDCR TADR TBDR TCDR TDDR SCR UCR RSR TSR UDR General Purpose I/O Register Active Edge Register Data Direction Register Interrupt Enable Register A Interrupt Enable Register B Interrupt Pending Register A Interrupt Pending Register B Interrupt In-service Register A Interrupt In-service Register B Interrupt Mask Register A Interrupt Mask Register B Vector Register Timer A Control Register Timer B Control Register Timers C and D Control Register Timer A Data Register Timer B Data Register Timer C Data Register Timer D Data Register Synchronous Character Register USART Control Register Receiver Status Register Transmitter Status Register USART Data Register Abbreviation Register Name Note : Hex addresses assume that RS1 connects with A1, RS 2connects wi th A2, etc.. . and that DS is connected t o LDS on the 68000 or DS is connect to DS on the 68008. 3/42 (R) TS68HC901 Figure 3 : PDIP Pin connection Figure 4 : PLCC Pin connection Pin 48 47 1 35 MOTOROLA 6800 Type CS E R/W VSS MOTOROLA Multiplexed CS DS R/W AS INTEL CS RD WR ALE PIN DESCRIPTION GND : VCC : R/W : Ground +5 volts ( 5%) Read/Write (input). This input defines a data transfert as a Read (High) or Write (Low) cycle. This signal is used as WR with an Intel processor type. DTACK : This output signals the completion of the operation phase of a bus cycle to the processor. If the bus cycle is a processor read, the CMFP asserts DTACK to indicate that the information on the Data bus is valid. If the bus cycle is a processor to the CMFP, DTACK acknowledges the acceptance of the data by the CMFP. DTACK will be asserted only by an CMFP that has CS or IAK (and IEI) asserted. This signal is not used with a 6800 processor type. CS : Chip Select (input, active low). CS is used to select the TS68HC901 CMFP for accesses to the internal registers. CS and IACK must not be asserted at the same time. Data Stobe (input, active low).This Input is part of the internal chip select and interrupt acknowledge functions. The CMFP must be located on the lower portion of the 16-bit data-bus so that the vector number passed to the processor during an interrupt acknowledge cycle will be located in the low byte of the data word. As a result, DS must be connected to the processor's lower data strobe if vectored interrupt are to be used. Note that this forces all registers to be located at odd addresses and latches data on the rising edge for writes. This signal is used as RD with an Intel processor type. DS : 4/42 (R) TS68HC901 RS1-RS5: Register Address Bus (inputs). The ad(A1-A5) dress bus is used to address one of the internal registers during a read or write cycle. D0-D7 : Data Bus (bi-directional, tri-stateable). This bus is used to receive data from or transmit data to the MFP's internal registers during a processor read or write cycle. During an interrupt acknowledge cycle, the data bus is used to pass a vector number to the processor. Since the MFP is an 8-bit peripheral, the MFP could be located on either the upper or lower portion of the 16-bit data bus (even or odd address). However, during an interrupt acknowledge cycle, the vector number passed to the processor must be located in the low byte of the data word. As a result, D0-D7 of the MFP must be connected to the low eight bits of the processor data bus, placing MFP registers at odd addresses if vectored interrupt are to be used. CLK : The clock input is a single-phase TTL compatible signal used for internal timing . This input should not be gated off at any time and must conform to minimum and maximum pulse width times. The clock is not necessarily the system clock in frequency nor phase. When the bus is multiplexed (MPX=1), an address strobe signal is connected to this pin. In the non multiplexed mode (MPX=0), this input is connected to the system clock when used with a 68000 processor type or to VSS (0VDC) when used with a 6800 processor type. RESET : Device reset. (input, active low). Reset disables the USART receiver and transmitter, stops all timers and forces the timer outputs low, disables all interrupt channels and clears any pending interrupts. The General Purpose Interrupt/I/O lines will be placed in the tri-state input mode. All internal registers (except the timer, USART data registers, and transmit status register) will be cleared. MPX : This input selects the data bus mode: MPX = 0 : non multiplexed mode MPX = 1 : multiplexed mode. The register select lines RS1-RS5 and the data bus D0-D7 are multiplexed. An address strobe must be connected to the CLK pin. TR : IRQ : Interrupt Request (output, active low, open drain). This output signals the processor that an interrupt is pending from the CMFP. These are 16 interrupt channels that can generate an interrupt request. Clearing the interrupt pending registers (IPRA and IPRB) or clearing the interrupt mask registers (IMRA and IMRB) will cause IRQ to be negated. IRQ will also be negated as the result of an interrupt acknowledge cycle, unless additional i nterrupts are pending in the CM FP. Ref er to paragraph INTERRUPTS for further information. Interrupt Acknowledge (input, active l ow ). IACK i s us ed t o s ignal t he TS68HC901 that the CPU is acknowledging an interrupt. CS and IACk must not be asserted at the same time. Interrupt Enable In (input, active low). IEI is used to signal the TS68HC901 that no higher priority device is requesting interrupt service. Interrupt Enable Out (output, active low). IEO is used to signal lower priority peripherals that neither the TS68HC901 nor another higher priority peripheral is requesting interrupt service. Ge neral Purpose Interrupt I/O lines. These lines may be used as interrupt inputs and/or I/O lines. When used asinterrupt inputs, their active edge is programmable. A data direction register is used to define which lines are to be Hi-Z inputs and which lines are to be push-pull TTL compatible outputs. Serial Output. This is the output of the USART transmitter. Serial Input. This is the input to the USART receiver. Receiver Clock. This input controls the serial bit rate of the USART receiver. Transmitter Clock. This input controls the serial bit rate of the USART transmitter. Receiver Ready. (output, active low) DMA output for receiver, which reflects the status of Buffer Full in port number 15. Transmitter Ready. (output, active low) DMA output for transmitter, which reflects the status of Buffer Empty in port number 16. 5/42 (R) IACK : IEI : IEO : I0-I7 : SO : SI : RC : TC : RR : TS68HC901 TAO,TBO, Timer Outputs. Each of the four timers TCO,TDO:has an output which can produce a square wave. The output will change states each timer cycle ; thus one full period of the timer out signal is equal to two timer cycles. TAO or TBO can be reset (logic "O") by a write to TACR, or TBCR respectively. XTAL1, XTAL2 : Timer Clock inputs. A crystal can be connected between XTAL1 and XTAL2, or XTAL1 can be driven with a TTL level clock. When driving XTAL1 with a TTL level clock, XTAL2 must be allowed to float. When using a crystal, external capacitors are required. See figure 35. All chip accesses are independent of the timer clock. TAI,TBI : Timer A, B inputs. These inputs are control signals for timers A and B in the pulse width measurement mode and event count mode. These signals generate interrupts at the same priority level as the general purpose I/O interrupt lines I4 and I3, respectively. I4 and I3 do not have interrupt capability when the timers are operated in the pulse width measurement mode or the event count mode - under these conditions I4 and I3 may only be used for I/O. Refer to paragraph TIMERS for further information. SIGNAL SUMMARY. Signal Name Power Input Ground Clock Chip Select Data Strobe Read/Write Data tranfer Acknowledge Register Select Bus Data Bus Reset Interrupt Request Interrupt Acknowledge Interrupt Enable In Interrupt Enable Out General Purpose I/O - Interrupt Lines Timer Clock Timer Inputs Timer Outputs Serial Input Serial Output Receiver Clock Transmitter Clock Receiver Ready Transmitter Ready MPX Mnemonic VCC GND CLK CS DS R/W DTACK RS1-RS5 D0-D7 RESET IRQ IACK IEI IEO I0-I7 XTAL1, XTAL2 TAI, TBI TAO, TBO, TCO, TDO SI SO RC TC RR TR MPX I/O Input Input Input Input Input Input Output Input I/O Input Output Input Input Output I/O Input Input Output Input Output Input Input Output Output Input Active High Low N/A Low Low Read-High / Write-Low Low N/A N/A Low Low Low Low Low N/A High N/A N/A N/A N/A N/A N/A Low Low N/A 6/42 (R) TS68HC901 BUS OPERATION The following paragraphs explain the control signals and bus operation during data transfer operations and reset. DATA TRANSFER OPERATIONS. Transfer of data between devices involves the following pins: Register Select Bus - RS5 through RS1 Data Bus - D0 through D7 Control Signals The address and data buses are separate parallel buses used to transfer data using an asynchronous bus structure. In all cycles, the bus master assumes responsibility for deskewing all signals it issues at both the start and end of a cycle. Additionally, the bus master is responsible for deskewing the acknowledge and data signals from the peripheral devices. Read Cycle. To read a CMFP register, CS and DS must be asserted, and R/W must be high. The CMFP will place the content of the register which is selected by the register select bus (RS1 through RS5) on the data bus (D1 through D7) and then assert DTACK. The register addresses are shown on Figure 2. After the processor has latched the data, DS is negated. The negation of either CS or DS will terminate the read operation. The CMFP will drive DTACK High and place it in the high-impedance state. The timing for a read cycle is shown in figure 21. Write Cycle. To write a register CS and DS must be asserted, and R/W must be low. The CMFP will decode the address bus to determine which register is selected. Then the register will be loaded with the contents of the data bus and DTACK will be asserted. When the processor recognizes DTACK, DS will be negated. The write cycle is terminated when either CS or DS is negated. The CMFP will drive DTACK high and place it in the high-impedance state. The timing for a write cycle is shown in figure 22. INTERRUPT ACKNOWLEDGE OPERATION. The CMFP has 16 interrupt sources, eight internal and eight external. When an interrupt request is pending, the CMFP will assert IRQ. In a vectored interrupt scheme, the processor will acknowledge the interrupt request by performing an interrupt acknowledge cycle. IACK and DS will be asserted. The CMFP responds to the IACK signal by placing a vector number on the lower eight bits of the data bus. This vector number corresponds to the IRQ handler for the particular interrupt requesting service. The format of this vector number is given in figure 6. When the CMFP asserts DTACK to indicate that valid data is on the bus, the processor will latch the data and terminate the bus cycle by negating DS. When either DS or IACK are negated, the CMFP will terminate the interrupt acknowledge operation by driving DTACK high and placing it in the high-impedance state. Also, the data bus will be placed in the high-impedance state. IRQ will be negated as a result of the IACK cycle unless additional interrupts are pending. The CMFP can be part of a daisy-chain interrupt structure which allows multiple CMFPs to be placed at the same interrupt level by sharing a common IACK signal. A daisy-chain priority scheme is implemented with IEI and IEO signals. IEI indicates that no higher priority device is requesting interrupt service. IEO signals lower priority devices that neither this device nor any higher priority devices is requesting service. To daisy-chain CMFPs, the highest priority CMFP has its IEI tied low and successive CMFPs have their IEI connected to the next higher priority device's IEO. Note that when the daisy-chain 7/42 (R) TS68HC901 interrupt structure is not implemented, the IEI of all CMFPs must be tied low. When the processor initiates an interrupt acknowledge cycle by driving IACK and DS, the CMFP whose IEI is low may respond with a vector number if interrupt is pending. If this device does not have a pending interrupt, IEO is asserted which allows the next lower priority device to respond to the interrupt acknowledge. When an CMFP propagates IEO, it will not drive the data bus nor DTACK during the interrupt acknowledge cycle. The timing for an IACK cycle is shown in figure 23 and 24. RESET OPERATION The reset operation will initialize the CMFP to a known state. The reset operation requires that the RESET input be asserted for a minimum of two microseconds. During a device reset condition, all internal CMFP registers are cleared except for the timer data registers (TADR, TBDR, TCDR and TDDR), the USART data register (UDR), the transmitter status register (TSR) and the interrupt vector register. All timers are stopped and the USART receiver and transmitter are disabled. The interrupt channels are also disabled and any pending interrupts are cleared. In addition, the general purpose interrupt I/O lines are placed in the high- impedance input mode and the timer outputs are driven low. External CMFP signals are negated. The interrupt vector register is initialized to a 0Fh. NON MULTIPLEXED MODE In this mode, the MPX input must be set to zero, and the TS68HC901 can be used with a 68000 processor type or a 6800 processor type. Refer to figure 21 to 24 for the electrical characteristics. With a 6800 processor type the DS pin is connected to the E signal of the processor, the DTACK signal is not used and the CLK must be zeroed. MULTIPLEXED MODE The CMFP can be used either on a MOTOROLA or INTEL bus type. In this case the MPX pin is connected to Vcc. The table page 4 gives the signification of the different signals used. A dummy access to the TS68HC901 has to be done before any valid access in order to set up the internal logic of sampling. 8/42 (R) TS68HC901 INTERRUPT STRUCTURE In a 68000 system, the CMFP will be assigned to one of the seven possible interrupt levels. All interrupt service requests from the CMFP's 16 interrupt channels will be presented at this level. Although, as an interrupt controller, the CMFP will internally prioritize its 16 interrupt sources. Additional interrupt sources may be placed at the same interrupt level by daisy-chaining multiple CMFPs. The CMFPs will be prioritized by their position in the chain. INTERRUPT PROCESSING Each CMFP provides individual interrupt capability for its various functions. When an interrupt is received on one of the external interrupt channels or from one of the eight internal sources, the CMFP will request interrupt service. The 16 interrupt channels are assigned a fixed priority so that multiple pending interrupts are serviced according to their relative importance. Since the CMFP can internally generate 16 vector numbers, the unique vector number which corresponds to the highest priority channel that as a pending interrupt is presented to the processor during an interrupt acknowledge cycle. This unique vector number allows the processor to immediately INTERRUPT VECTOR NUMBER FORMAT During an interrupt acknowledge cycle, a unique 8bit vector number is presented to the system which corresponds to the specific interrupt source which is requesting service. The format of the vector is shown in figure 6. The most significant four bits of the interrupt vector number are user programmable. These bits are set by writing the upper four bits of the vector register which is shown in figure 7. The low order bits are generated internally by the TS68HC901. Note that the binary channel number shown in figure 5 corresponds to the low order bits of the vector number associated with each channel. Figure 5 : Interrupt Channel Prioritization Figure 9 : Interrupt Channel Priority HIGHEST begin execution of the interrupt handler for the interrupt source, decreasing interrupt latency time. INTERRUPT CHANNEL PRIORITIZATION The 16 interrupt channels are prioritized as shown in figure 5. General purpose interrupt 7 (I7) is the highest priority interrupt channel and I0 is the lowest priority channel. Pending interrupts are presented to the CPU in order of priority unless they have been masked off. By selectively masking interrupts, the channel are in effect re-prioritized. Prioritization Description General Purpose Interrupt General Purpose Interrupt Timer A Receive Buffer Full Receive Error Transmit Buffer Empty Transmit Error Timer B General Purpose Interrupt General Purpose Interrupt Timer C Timer D General Purpose Interrupt General Purpose Interrupt General Purpose Interrupt General Purpose Interrupt 7(I7) 6(I6) 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Channel 5(I5) 4(I4) LOWEST 3(I3) 2(I2) 1(I1) 0(I0) 9/42 (R) TS68HC901 Figure 6 : V7 V6 V5 V4 IV3 IV2 IV1 IV0 V7-V4 IV3-IV0 The four most significant bits are copied from the register These bits are supplied by the CMFP. They are the binary channel number of the highest priority channel that is requesting interrupt service. Figure 7 : 7 VECTOR REGISTER V6 V5 V4 S 0* 0* 0 0* VR (17h) V7 Writing 0 : CLEARED Writing 1 : SET CLEARED on RESET V7-V4 S The upper four bits of the vector register are written by the user. These bits become the most significant four bits of the interrupt vector number. In-Service Register Enable. When the S bit is zero, the CMFP is in the automatic end-of-interrupt mode and the In-Service register bits are forced low. When the S bit is a one, the CMFP is in the software end-of-interrupt mode and the In-Service register bits are enabled. Unused bits, read as zero. * Figure 8 : Daisy Chaining TS68HC901 TS68HC901 TS68HC901 10/42 (R) TS68HC901 DAISY-CHAINING CMFPs As an interrupt controller, the TS68HC901 CMFP will support eight external interrupt sources in addition to its eight internal interrupt sources. When a system requires more than eight external interrupt sources to be placed at the same interrupt level, sources may be added to the prioritized structure by daisy-chaining CMFPs. Interrupt sources are prioritized internally within each CMFP and the CMFPs are prioritized by their position in the chain. Unique vector numbers are provided for each interrupt sources. The IEI and IEO signals implement the daisy-chained interrupt structure. The IEI of the highest priority CMFP is tied low and the IEO output of this device is tied to the next highest priority CMFP's IEI. The IEI and IEO signals are daisy-chained in this manner for all CMFPs in the chain, with the lowest priority CMFP's IEO left unconnected. A diagram of an interrupt daisy-chain is shown in figure 8. Daisy-chaining requires that all parts in the chain have a common IACK. When the common IACK is asserted during an interrupt acknowledge cycle, all parts will prioritize interrupts in parallel. When the IEI signal to a CMFP is asserted, the part may respond to the IACK cycle if it requires interrupt service. Otherwise, the part will assert IEO to the next lower priority device. Thus, priority is passed down the chain via IEI and IEO until a part which has appending interrupt is reached. The part with the pending interrupt passes a vector number to the processor and does not propagate IEO. Figure 9a : Figure 9b : 11/42 (R) TS68HC901 INTERRUPT CONTROL REGISTERS CMPF interrupt processing is managed by the interrupt enable registers A and B, interrupt pending registers A and B, and interrupt mask registers A and B. These registers allow the programmer to enable or disable individual interrupt channels, mask individual interrupt channels, and access pending interrupt status information. In-service registers A and B allow interrupts to be nested as described hereafter. The interrupt control registers are shown in figure 10. INTERRUPT ENABLE REGISTERS The interrupt channels are individually enabled or disabled by writing a one or zero, respectively, to the appropriate bit of interrupt enable register A (IERA) or interrupt enable register B (IERB). The processor may read these registers at any time. When a channel is enabled, interrupts received on the channel will be recognized by the CMFP and IRQ will be asserted to the processor, indicating that interrupt service is required. On the other hand, a disabled channel is completely inactive; interrupts received on the channel are ignored by the CMFP. Writing a zero to a bit of interrupt enable register A or B will cause the corresponding bit of interrupt pending register A or B to be cleared. This will terminate all interrupt service requests for the channel and also negate IRQ, unless interrupts are pending from other sources. Disabling a channel, however, does not affect the corresponding bit in interrupt in-service registers A or B. So, if the CMFP is in the software end-of-interrupt mode and an interrupt is in service when a channel will remain set until cleared by software. INTERRUPT PENDING REGISTERS When an interrupt is received on an enabled channel, the corresponding interrupt pending bit is set in interrupt pending register A or B (IPRA or IPRB). In a vectored interrupt scheme, this bit will be cleared when the processor acknowledges the interrupting channel and the CMFP responds with a vector number. In a polled interrupt system, the interrupt pending registers must be read to determine the interrupting channel and then the interrupting pending bit is cleared by the interrupt handling routine without performing an interrupt acknowledge sequence. A single bit of the interrupt pending registers is cleared in software by writing ones to all bit positions except the bit to be cleared. Note that writing ones to IPRA and IPRB has no effect on the contents of the register. A single bit of the interrupt pending registers is also cleared when the corresponding channel is disabled by writing a zero to the appropriate bit of IERA or IERB. INTERRUPT MASK REGISTERS Interrupts are masked for a channel by clearing the appropriate bit in interrupt mask register A or B (IMRA or IMRB). Even though an enabled channel is masked, the channel will recognize subsequent interrupts and set its interrupt pending bit. However, the channel is prevented from requesting interrupt service (IRQ to the processor) as long as the mask bit for that channel is cleared. If a channel is requesting interrupt service at the time that its corresponding bit in IMRA or IMRB is cleared, the request will cease and IRQ will be negated, unless another channel is requesting interrupt service. Later, when the mask bit is set, any pending interrupt on the channel will be processed according to the channel's assigned priority. IMRA and IMRB may be read at any time. 12/42 (R) TS68HC901 Figure 10 : 7 INTERRUPT ENABLE REGISTERS GPIP6 TIMER A RCV Buffer full RCV Error XMIT Buffer Empty XMIT Error 0 TIMER B IERA (07h) GPIP7 IERB (09h) GPIP5 GPIP4 TIMER C TIMER D GPIP3 GPIP2 GPIP1 GPIP0 7 INTERRUPT PENDING REGISTERS GPIP6 TIMER A RCV Buffer full RCV Error XMIT Buffer Empty XMIT Error 0 TIMER B IPRA (0Bh) GPIP7 IPRB (0Dh) GPIP5 GPIP4 TIMER C TIMER D GPIP3 GPIP2 GPIP1 GPIP0 Wri ti ng 0 : CLEAR Wri ti ng 1 : UNCHANGED 7 INTERRUPT IN-SERVICE REGISTERS GPIP6 TIMER A RCV Buffer full RCV Error XMIT Buffer Empty XMIT Error 0 TIMER B ISRA (0Fh) GPIP7 ISRB (11h) GPIP5 GPIP4 TIMER C TIMER D GPIP3 GPIP2 GPIP1 GPIP0 7 INTERRUPT MASK REGISTERS GPIP6 TIMER A RCV Buffer full RCV Error XMIT Buffer Empty XMIT Error 0 TIMER B IMRA (13h) GPIP7 IMRB (15h) GPIP5 GPIP4 TIMER C TIMER D GPIP3 GPIP2 GPIP1 GPIP0 Writing 0 : MASKE D Writing 1 : UNMASKED 13/42 (R) TS68HC901 NESTING CMFP INTERRUPTS In a 68000 vectored interrupt system, the CMFP is assigned to one of seven possible interrupt levels. When an interrupt is received from the CMFP, an interrupt acknowledge for that level is initiated. Once an interrupt is recognized at a particular level, interrupts at that same level or below are masked by 68000. As long as the processor's interrupt mask is unchanged, the 68000 interrupt structure will prohibit the nesting of interrupts at the same interrupt level. However, additional interrupt requests from the CMFP can be recognized before a previous channel's interrupt service routine is completed by lowering the processor's interrupt mask to the next lower interrupt level within the interrupt handler. When nesting CMFP interrupts, it may be desirable to permit interrupts on any CMFP channel, regardless of its priority, to preempt or delay interrupt processing of an earlier channel's interrupt service request. Or, it may be desirable to only allow subsequent higher priority channel interrupt requests to supersede previously recognized lower priority interrupt requests. The CMFP interrupt structure provides this flexibility by offering two end-of-interrupt options for vectored interrupt schemes. Note that the end-of-interrupt modes are not active in a polled interrupt scheme. SELECTING THE END-OF-INTERRUPT MODE In a vectored interrupt scheme, the CMFP may be programmed to operate in either the automatic endof-interrupt mode or the software end-of-interrupt mode. The mode is selected by writing the S bit of the vector register (see figure 7). When the S bit is programmed to a one, the CMFP is placed in the software end-of-interrupt mode and when the S bit is a zero, all channels operate in the automatic endof-interrupt mode. AUTOMATIC END-OF-INTERRUPT When an interrupt vector number is passed to the processor during an interrupt acknowledge cycle, the corresponding channel's interrupt pending bit is cleared. In the automatic end-of-interrupt mode, no further history of the interrupt remains in the CMFP. The in-service bits of the interrupt in-service registers (ISRA and ISRB) are forced low. Subsequent interrupts which are received on any CMFP channel will generate an interrupt request to the processor, even if the current interrupt's service routine has not been completed. SOFTWARE END-OF-INTERRUPT In the software end-of-interrupt mode, the channel's associated interrupt pending bit is cleared and in addition, the channel's in-service bit of in-service register A or B is set when its vector number is passed to the processor during an IACK cycle. A higher priority channel may subsequently request interrupt service and be acknowledged, but as long as the channel's in-service bit is set, no lower priority channel may request interrupt service nor pass its vector during an interrupt acknowledge sequence. While only higher priority channels may request interrupt service, any channel can receive an interrupt and set its interrupt pending bit. Even the channel whose in-service bit is set can receive a second interrupt. However, no interrupt service request is made until its in-service bit is cleared. The in-service bit for a particular channel can be cleared by writing a zero to its corresponding bit in ISRA or ISRB and ones to all other bit positions. Since bits in the in-service registers can only be cleared in software and not set, writing ones to the register does not alter their contents. ISRA and ISRB may be read at any time. 14/42 (R) TS68HC901 GENERAL PURPOSE INPUT/OUTPUT INTERRUPT PORT The general purpose interrupt input/output (I/O) port (GPIP) provides eight I/O lines (I0 through I7) that may be operated as either inputs or outputs under software control. In addition, these lines may optionally generate an interrupt on either a positive transition or negative transition of the input signal. The flexibility of the GPIP allows it to be configured as an 8-Bit I/0 port or for bit I/O. Since interrupts are enabled on a bit-by-bit basis, a subset of the GPIP could be programmed as handshake lines or the port could be connected to as many as eight external interrupt sources, which would be prioritized by the CMFP interrupt controller for interrupt service. 6800 INTERRUPT CONTROLLER The CMFP interrupt controller is particularly useful in a system which has many 6800-type devices. Typically, in a vectored 68000 system, 6800-type peripherals use the autovector which corresponds to their assigned interrupt level since they do not provide a vector number in response to an AC cycle. The autovector interrupt handler must then poll all 6800-type devices at that interrupt level to determine which device is requesting service. However, by tying the IRQ output from a 6800-type device to the general purpose I/O interrupt port (GPIP) of a CMFP, a unique vector number will be provided to the processor during an interrupt acknowledge cycle. This interrupt structure will significantly reduce interrupt latency for 6800-type devices and other peripheral devices which do not support vector-by-device. GPIP CONTROL REGISTERS The GPIP is programmed via three control registers shown in figure 11. These registers control the data direction provide user access to the port, and specify the active edge for each bit of the GPIP which will produce an interrupt. These registers are described in detail in the following paragraphs. GPIP DATA REGISTER The general purpose I/O data register is used to input or output data to the port. When data is written to the GPIP data register, those pins which are defined as inputs will remain in the high-impedance state. Pins which are defined as outputs will assume the state (high or low) of their corresponding bit in the data register. When the GPIP is read, data will be passed directly from the bits of the data register for pins which are defined as outputs. Data from pins defined as inputs will come from the input buffers. ACTIVE EDGE REGISTER The active edge register (AER) allows each of the GPIP lines to produce an interrupt on either a oneto-zero or a zero-to-one transition. Writing a zero the appropriate edge bit of the active edge register causes the associated input to generate an interrupt on the one-to-zero transition. Writing a one to the edge bit will produce an interrupt on the zero-to-one transition of the corresponding GPIP line. 15/42 (R) TS68HC901 Figure 11 : 7 AER (03h) GPIP7 GPIP6 GPIP5 ACTIVE EDGE REGISTER GPIP4 GPIP3 GPIP2 GPIP1 0 GPIP0 1 = RISING 2 = FALLING DATA DIRECTION REGISTER DDR (05h) GPIP7 GPIP6 GPIP5 GPIP4 GPIP3 GPIP2 GPIP1 GPIP0 1 = OUTPUT 2 = INPUT GENERAL PURPOSE I/O DATA REGISTER GPIP (01h) GPIP7 GPIP6 GPIP5 GPIP4 GPIP3 GPIP2 GPIP1 GPIP0 Note The transition detector is an exclusive-OR gate whose inputs are the edge bit and the input buffer. As a result, writing the EAR may cause an interruptproducing transition, depending upon the state of the input. So, the AER should be configured before enabling interrupts via the interrupt enable registers (IERA and IERB). Also, changing the edge bit while interrupts are enabled may cause an interrupt on the corresponding channel. DATA DIRECTION REGISTER The data direction register (DDR) allows the programmer to define I0 through I7 as inputs or outputs by writing the corresponding bit. When a bit of the data direction register is written as a zero, the corresponding interrupt I/O pin will be a high-impedance input. Writing a one to any bit of the data direction register will cause the corresponding pin to be configured as a push-pull output. 16/42 (R) TS68HC901 TIMERS The CMFP contains four 8-bit timers which provide many functions typically required in microprocessor systems. The timers can supply the baud rate clocks for the on-chip serial I/O channel, generate periodic interrupts, measure elapsed time, and count signal transitions. In addition, two timers have waveform generation capability. All timers are prescaler/counter timers with a common independent clock input (XTAL1 or XTAL2) and are not required to be operated from the system clock. Each timer's output signal toggles when the timer's main counter times out. Additionally, timers A and B have auxiliary control signals which are used in two of the operation modes. An interrupt channel is assigned to each timer and when the auxiliary control signals are used, a separate interrupt channel will respond to transitions on these inputs. OPERATION MODES Timers A and B are full function timers which, in addition to the delay mode, operate in the pulse width measurement mode and the event count mode. Timers C and D are delay timers only. A brief discussion of each of the timer modes follows. DELAY MODE OPERATION All timers may operate in the delay mode. In this mode, the prescaler is always active. The prescaler specifies the number of timer clock cycles which must elapse before a count pulse is applied to the main counter. A count pulse causes the main counter to decrement by one. When the timer has decremented down to 01 (hexadecimal), the next count pulse will cause the main counter to be reloaded from the timer data register and a time out pulse will be produced. This time out pulse is coupled to the timer's interrupt channel and, if the channel is enabled, an interrupt will occur. The time out pulse also causes the timer output pin to toggle. The output will remain in this new state until the next time out pulse occurs. For example, if delay mode with a divide-by-10 prescaler is selected and the timer data register is loaded with 100 (decimal), the main counter will decrement once every 10 timer clock cycles. After 1,000 timer clocks, a time out pulse will be produced. This time out pulse will generate an interrupt if the channel is enabled (IERA, IERB) and in addition, the timer's output line will toggle. The output line will complete one full period every 2,000 cycles of the timer clock. If the prescaler value is changed while the timer is enabled, the first time out pulse will occur at an indeterminate time no less than one nor more than 200 timer clock cycles. Subsequent time out pulses will then occur at the correct interval. If the main counter is loaded with 01 (hexadecimal), a time out pulse will occur every time the prescaler presents a count pulse to the main counter. If the main counter is loaded with 00, a time out pulse will occur every 256 count pulses. PULSE WIDTH MEASUREMENT OPERATION Besides the delay mode, timers A and B may be programmed to operate in the pulse width measurement mode. In this mode an auxiliary control input is required ; timers A and B auxiliary input lines are TAI and TBI. Also, in the pulse width measurement mode, interrupt channels normally associated with I4 and I3 will respond to transitions on TAI and TBI, respectively. General purpose lines I3 and I4 may still be used for I/O. A conceptual circuit of the timers 17/42 (R) TS68HC901 Figure 12 : in the pulse width measurement mode is shown in Figure 12. The pulse width measurement mode functions similarly to the delay mode, with the auxiliary control signal acting as an enable to the timer. When the control signal is active, the prescaler and main counter are allowed to operate. When the control signal is negated, the timer is stopped. So, the width of the active pulse on TAI or TBI is measured by the number of timer counts which occur while the timer is allowed to operate. The active state of the auxiliary input line is defined by the associated interrupt channel's edge bit in the active edge register (AER). GPIP4 of the AER is the edge bit associated with TAI and GPIP3 is associated with TBI. When the edge bit is a one, the auxiliary input will be active high, enabling the timer while the input signal is at a high level. If the edge bit is low, the auxiliary input will be active low and the timer will operate while the input signal is at a low level. The state of the active edge bit also specifies whether a zero-to-one transition or a one-to-zero transition of the auxiliary input pin will produce an interrupt when the interrupt channel is enabled. In normal operation, programming the active edge bit to a one will produce an interrupt on the zero-to-one transition of the associated input signal. Alternately, pro- gramming the edge bit to a zero will produce an interrupt on the one-to-zero transition of the input signal. However, in the pulse width measurement mode, the interrupt generated by a transition on TAI or TBI will occur on the opposite transition as that normally defined by the edge bit. For example, in the pulse width measurement mode, if the edge bit is a one, the timer will be allowed to run while the auxiliary input TAI is high. When TAI transitions from high to low, the timer will stop and, if the interrupt channel is enabled, an interrupt will occur. By having the interrupt occur on the oneto-zero transition instead of the zero-to-one transition, the processor will be interrupted when the pulse being measured has terminated and the width of the pulse is available from the timer. Therefore, the timers act like a divide-by-prescaler that can be programmed by the timer data register and the timer's A and B control register. After reading the contents of the timer, the main counter must be reinitialized by writing to the timer data register to allow consecutive pulses to be measured. If the timer is written after the auxiliary input signal is active, the timer will count from the previous contents of the timer data register until it counts through 01 (hexadecimal). At the time, the main counter is loaded with the value from the timer data register, a time out pulse is generated which will tog- 18/42 (R) TS68HC901 gle the timer output, and an interrupt may be optionally generated on the timer interrupt channel. Note that the pulse width measured will include counts from before the main counter was reloaded. If the timer data register is written while the pulse is transitioning to the active state, an indeterminate value may be written into the main counter. Once the timer is reprogrammed for another mode, interrupts will again occur as normally defined by the edge bit. Note that an interrupt may be generated as the result of placing the timer into the pulse width measurement mode or by reprogramming the timer for another mode. Also, an interrupt may be generated by changing the state of the edge bit while in the pulse width measurement mode. EVENT COUNT MODE OPERATION In addition to the delay mode and the pulse width measurement mode, timers A and B may be programmed to operate in the event count mode. Like the pulse width measurement mode, the event count mode also requires an auxiliary input signal, TAI or TBI, and the interrupt channels normally associated with I4 and I3 will respond to transitions on TAI and TBI respectively. General purpose lines I3 and I4 only function as I/O ports. In the event count mode the prescaler is disabled, allowing each active transition on TAIand TBI to produce a count pulse. The count pulse causes the main counter to decrement by one. When the timer counts through 01 (hexadecimal), a time out pulse is generated which will cause the output signal to toggle and may optionally produce an interrupt via the associated timer interrupt channel. The timer's main counter is also reloaded from the timer data register. To count transitions reliably, the input signal may only transition once every four timer clock periods. For this reason, the input signal must have a maximum frequency equal to one-fourth that of the timer clock. The active edge of the auxiliary input signal is defined by the associated interrupt channel's edge bit. GPIP4 of the AER specifies the active edge for TAI and GPIP3 defines the active edge for TBI. When the edge bit is programmed to a one, a count pulse will be generated on the zero-to-one transition of the auxiliary input signal. When the edge bit is programmed to a zero, a count pulse will be generated on the one-to-zero transition. Also, note that changing the state of the edge bit while the timer is in the event count mode may produce a count pulse. Besides generating a count pulse, the active transition of the auxiliary input signal will also produce an interrupt on the I3 or I4 interrupt channel, if the interrupt channel is enabled. Typically, in the event count mode, these channels are not enabled since the timer is automatically counting transitions on the input signal. If the interrupt channel is enabled, the number of transitions could be counted in the interrupt routine without requiring the use of the timer. TIMER REGISTERS The four timers are programmed via three control registers and four timer data registers. Control registers TACR and TBCR and timer data registers TADR and TBDR (refer to figure 5.1) are associated with timers A and B respectively. Timers C and D are controlled by the control register TCDCR and the data registers TCDR and TDDR (refer to Figure 13). TIMER DATA REGISTERS Each timer's main counter is an 8-bit binary down counter. The value of the main counter may be read at any time by reading the timer's data register. The information read is the value of the counter which was captured on the last low-to-high transition of the DS pin. The main counter is initialized by writing to the timer's data register. If the timer is stopped, data is loaded simultaneously into both the timer data register and the main counter. If the timer data register is written while the timer is enabled, the value is not loaded into the timer until the timer counts through 01 (hexadecimal). Writing the timer data register while the timer is counting through 01 (hexadecimal) will cause an indeterminate value to be loaded into the timer's main counter. The four data registers are shown in Figure 13. TIMER CONTROL REGISTERS Bits in the timer control registers select the operation mode, select the prescaler value, and disable the timers. Timer control registers TACR and TBCR also have bits which allow the programmer to reset out- 19/42 (R) TS68HC901 Figure 13 : 7 (a) TIMER A DATA REGISTER D6 D5 D4 D3 D2 D1 0 TADR (1Fh) D7 D0 (b) TIMER B DATA REGISTER TBDR (21h) D7 D6 D5 D4 D3 D2 D1 D0 (c) TIMER C DATA REGISTER TCDR (23h) D7 D6 D5 D4 D3 D2 D1 D0 (d) TIMER D DATA REGISTER TDDR (25h) D7 D6 D5 D4 D3 D2 D1 D0 CLEARED on RESE T Writing 0 : CLEARED Wri ting 1 : SET 20/42 (R) TS68HC901 Figure 14 : 7 TIMER A CONTROL REGISTER 0* 0* TA0 RESET AC3 AC2 AC1 0 AC0 TACR (19h) 0* TIMER B CONTROL REGISTER TBCR (1Bh) 0* 0* 0* TB0 RESET BC3 BC2 BC1 BC0 CLEARED on RESET 0* Unused bits, read as zero. RESET Timer's A and B output lines (TA0 and TB0) may be forced low at any time by writing a one TA0/TB0 to the reset location in TACR and TBCR, respectively. The output will be held low only during the write operation ; at the conclusion of the operation the output will be allowed to toggle in response to a time-out pulse. When resetting TA0 and TB0, the remaining bits in the control register must be written with their previous value to avoid altering the operation mode. SET: End of write cycle which clears the bit CLEARED: MPUwrites a zero AC3-AC0 These bits are decoded to determine the timer operation mode. BC3-BC0 AC3 BC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 AC2 BC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 AC1 BC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 AC0 BC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Operation Mode Timer Stopped* Delay Mode, / 4 Prescaler Delay Mode, / 10 Prescaler Delay Mode, / 16 Prescaler Delay Mode, / 50 Prescaler Delay Mode, / 64 Prescaler Delay Mode, / 100 Prescaler Delay Mode, / 200 Prescaler Event Count Mode Pulse Width Mode, / 4 Prescaler Pulse Width Mode, / 10 Prescaler Pulse Width Mode, / 16 Prescaler Pulse Width Mode, / 50 Prescaler Pulse Width Mode, / 64 Prescaler Pulse Width Mode, / 100 Prescaler Pulse Width Mode, / 200 Prescaler * Regardless of the operation mode, counting is inhibited when the timer is stopped. The contents of the timer's main counter is not affected, although any residual count in the prescaler is lost. SET: End of write cycle which clears the bit CLEARED: MPUwrites a zero 21/42 (R) TS68HC901 Figure 15 : 7 TIMER C AND D CONTROL REGISTER CC2 CC1 CC0 0* DC2 DC1 0 DC0 TCDCR (1Dh) 0* CLEARED on RESET 0* Unused bits, read as zero. CC2-CC0 These bits are decoded to determine the timer operation mode. DC2-DC0 CC2 DC2 0 0 0 0 1 1 1 1 CC1 DC1 0 0 1 1 0 0 1 1 CC0 DC0 0 1 0 1 0 1 0 1 Operation Mode Timer Stopped* Delay Mode, / 4 Prescaler Delay Mode, / 10 Prescaler Delay Mode, / 16 Prescaler Delay Mode, / 50 Prescaler Delay Mode, / 64 Prescaler Delay Mode, / 100 Prescaler Delay Mode, / 200 Prescaler * Regardless of the operation mode, counting is inhibited when the timer is stopped. The contents of the timer's main counter is not affected, although any residual count in the prescaler is lost. SET: End of write cycle which clears the bit CLEARED: MPUwrites a zero 22/42 (R) TS68HC901 put lines TA0 and TB0. These control registers are shown in Figure 14. ASYNCHRONOUS FORMAT Variable word length and start / stop bit configurations are available under software control for asynchronous operation. The word length can be five to eight bits and one, one and one-half, or two stop bits can be selected. The user can also select odd, even, or no parity. For character lengths of less than eight bits, the assembled character will consist of the required number of data bits followed by zeros in the unused bit positions and a parity bit, if parity is enabled. In the asynchronous format, start bit detection is always enabled. New data is not shifted into the receive shift register until a zero bit is received. When the divide-by-16 clock mode is selected, the false start bit logic is also active. Any transition must be stable for three positive receive clock edges to be considered valid. Then a valid zero-to-one transition must not occur for at least eight additional positive clock edges. SYNCHRONOUS FORMAT When the synchronous character format is selected, the 8-bit synchronous character loaded into the synchronous character register is compared to received serial data until a match is found. Once synchronization is established, incoming data is clocked into the receiver. The synchronous word will be continuously transmitted during an underrun condition. All synchronous characters can be optionally stripped from the receive buffer. Figure 15 shows the synchronous character register. The synchronous character is typically written after the data word length is selected, since unused bits in the synchronous character register are zeroed out. When parity is enabled, synchronous word length is the data word length plus one. The CMFP will compute and append the parity bit for the synchronous word when a word length of eight is selected. However, if the word length is less than eight, Figure 16 : UNIVERSAL SYNCHRONOUS / ASYNCHRONOUS RECEIVER-TRANSMITTER The universal synchronous / asynchronous receiver-transmitter (USART) is a single full-duplex serial channel with a double-buffered receiver and transmitter. There are separate receive and transmit clocks and separate receive and transmit status and data bytes. The receive and transmit sections are also assigned separate interrupt channels. Each section has both a normal condition interrupt channel and an error condition interrupt channel. These channels can be optionally disabled from interrupting the processor and instead, DMA transfers can be performed using the receiver ready and transmitter ready external CMFP signals. CHARACTER PROTOCOLS The CMFP USART supports asynchronous and with the aid of a polynomial generator checker (PGC) supports byte synchronous character formats. These formats are selected independently of the divide-by-one and divide-by-16 clock modes. When the divide-by-one clock mode is selected, synchronization must be accomplished externally. The receiver will sample the serial data on the rising edge of the receiver clock. In the divide-by-16 clock mode, the data is sampled at mid-bit time to increase transient noise rejection. Also, when the divide-by-16 clock mode is selected, the USART resynchronization logic is enabled. This logic increases the channel's clock skew tolerance. When a valid transition is detected, an internal counter is reset to state zero. Transition checking is then inhibited until state four. Then at state eight, the previous state of the transition checking logic is clocked into the receive shift register. 7 USART DATA REGISTER D6 D5 D4 D3 D2 D1 0 D0 UDR (2Fh) D7 7 SYNCHRONOUS CHARACTER REGISTER D6 D5 D4 D3 D2 D1 0 D0 SCR (27h) D7 23/42 (R) TS68HC901 the user must determine the synchronous word parity and write it into synchronous character. The CMFP will then transmit the extra bit in the synchronous word as a parity bit. USART CONTROL REGISTER The USART control register (UCR) selects the clock mode and the character format for the receive and transmit sections. This register is shown in Figure 17. RECEIVER As data is received on the serial input line (SI), it is clocked into an internal 8-bit shift register until the specified number of data bits have been assembled. This character will then be transferred to the receive buffer, assuming that the last word in the receiver buffer has been read. This transfer produces a buffer full interrupt to the processor. Reading the receive buffer satisfies the buffer full condition and allows a next data word to be transferred to the receive buffer when it is assembled. The receive buffer is accessed by reading the USART data register (UDR). The UDR is simply an 8bit data register used when transferring data from the CMFP and CPU. Each time a word is transferred to the receive buffer, its status information is latched into the receiver status register (RSR). The RSR is not updated again until the data word in the receive buffer has been read. When a buffer full condition exists, the RSR should always be read before the receive buffer (UDR) to maintain the correct correspondence between data and flags. Otherwise, it is possible that after reading the UDR and prior to reading the RSR, a new word could be receive and transferred to the Figure 17 : 7 USART CONTROL REGISTER WL1 WL0 ST1 ST0 PE E/O 0 WU UCR (29h) CLK CLEARED on RESE T Writing 0 : CLEARED Wri ting 1 : SET receive buffer. Its associated flags would be latched into the RSR, over-writing the flags of the previous data word. Then when the RSR were read to access the status information for the first data word, the flags for the new word would be retrieved. CLK Clock Mode. When this bit is zero, data will be clocked into and out of the receiver and transmitter at the frequency of their respective clocks. When this bit is a one, data will be clocked into and out of the receiver and transmitter at one sixteenth the frequency of their respective clocks. Also, the receiver data transition resynchronization logic will be enabled. WL0, WL1 Word Length. These two bits specify the length of the data word exclusive of start bits, stop bits, and parity. ST0, ST1 Start/Stop Bit and Format Control. These two bits select the number of start and stop bits and also specify the character format. PE Parity Enable. When this bit is zero, no parity check will be made and no parity bit will be computed for transmission. When this bit is a one, parity will be checked by the receiver and parity will be calculated and inserted during data transmission. Note that parity is not automatically appended to the synchronous character for word lengths of less than eight bits. In this case, the parity should be written into the synchronous character register along with the synchronous word. E/0 WU ST1 Even/Odd Parity. When this bit is zero, odd parity is selected. When this bit is a one, even parity is selected. Bit 0 Reserved. Must be maintained at 0. ST0 Start Bits Stop Bits Format WL1 WL0 Word Length 24/42 (R) TS68HC901 SYNC 0 0 1 1 0 1 0 1 0 1 1 1 0 ASYN 1 C 11/2 ASYN C* 2 ASYN C 0 0 1 1 0 1 0 1 8 7 6 5 Bits Bits Bits Bits rated on the error channel only. However, if the error channel is disabled, an interrupt for an error condition will be generated on the buffer full interrupt channel along with interrupts produced by the buffer full condition. The receiver status register must always be read to determine which error condition produced the interrupt. (*) : Only used with divide-by-16 clock mode RECEIVER INTERRUPT CHANNELS The USART receive section is assigned two interrupt channels. One indicates the buffer full condition, while the other channel indicates an error condition. Error conditions include overrun, parity error, synchronous found, and break. These interrupting conditions correspond to the BF, OE, PE, and F/S or B bits of the receiver status register. These flags will function as described in 6.2.2. whether the receiver interrupt channels are enabled or disabled. While only one interrupt is generated per character received, two dedicated interrupt channels allow separate vector numbers to be assigned for normal and abnormal receiver conditions. When a received word has an error associated with it and the error interrupt channel is enabled, an interrupt will be gene- RECEIVER STATUS REGISTER The receiver status register contains the receive buffer full flag, the synchronous strip enable, the receiver enable, and various status information associated with the data word in the receive buffer. The RSR is latched each time a data word is transferred to the receive buffer. RSR flags cannot change again until the data word has been read. The exception is the character in progress flag which monitors when a new word is being assembled in the asynchronous character format. The receiver status register is shown in Figure 18. SPECIAL RECEIVE CONSIDERATIONS Figure 18 : 7 RECEIVER STATUS REGISTER OE PE FE F/S or B M/CIP SS 0 RE RSR (2Bh) BF CLEARE D on RESET Certain receive conditions relating to the overrun error flag and the break defect flag require further explanation. Consider the following examples : 1) A break is received while the receive buffer is full. This does not produce an overrun condition. Only the B flag will be set after the receiver buffer is read. 2) A new word is received and the receive buffer is full. A break is received before the receive buffer is read. Both the B and OE flags will be set when the buffer full condition is satisfied. BF Buffer Full. This bit is set when a received word is transferred to the receive buffer. This bit is cleared when the receive buffer is read by accessing the USART data register (UDR). This bit is read only. SET : Received word transferred to buffer CLEARED : Receive buffer read OE Overrun Error. An overrun error occurs when a received word is due to be transferred to the receive buffer, but the receive buffer is full. Neither the receive buffer nor the RSR is overwritten. The OE bit is set after the receive buffer full condition is satisfied by reading the UDR. This error condition will generate an interrupt to the processor. The OE bit is cleared by reading the RSR. New data words will not be assembled until the RSR is read. 25/42 (R) TS68HC901 Receiver Status Register (Continued) SET : Incoming word received and receive buffer full CLEARED : Receiver status register read PE Parity Error. This bit is set when the word transferred to the receive buffer has a parity error. This bit is cleared when the word transferred to the receive buffer does not have a parity error. SET : Word in receive buffer has a parity error CLEARED : Word in receive buffer does not have a parity error FE Frame Error. A frame error exists when a non-zero data word is not followed by a stop bit in the asynchronous character format. The FE bit is set when the word transferred to the receive buffer has a frame error. The FE bit is cleared when the word transferred to the receive buffer does not have a frame error. SET : Word in receive buffer has a frame error CLEARED : Word in receive buffer does not have a frame error F/S or B Found/Search or Break Detect. In the synchronous character format this bit can be set or cleared by software. When the bit is a zero, the USART receiver is placed in the search mode. The incoming data is compared to the synchronous character register (SCR) and the word length counter is disabled. The F/S bit will automatically be set when a match is found and the word length counter will be enabled. An interrupt will also be produced on the receive error channel. SET : Incoming word matches synchronous character CLEARED : MPU writes a zero or Incoming word does not match synchronous character In the asynchronous character format, this flag indicates a break condition. A break is detected when an all zero data word with no stop bit is received. The break condition continues until a non-zero data bit is received. The 8-bit is set when the word transferred to the receive buffer is a break indication. A break condition generates an interrupt to the processor. This bit is cleared when a non-zero data bit is received and the break condition has been acknowledged by reading the RSR at least once. An end of break interrupt will be generated when the bit is cleared. SET : Word in receive buffer is a break CLEARED : Break terminates and receiver status register read since beginning of break condition M or CIP Match/Character in Progress. In the synchronous format, this flag indicates that a synchronous character has been received. The M bit is set when the word transferred to the receive buffer matches the synchronous character register. The M bit is cleared when the word transferred to the receive buffer does not match the synchronous character register. SET : Word transferred to receive buffer matches the synchronous character CLEARED : Word transferred to receive buffer does not match synchronous character In the asynchronous character format, this flag indicates that a word is being assembled. The CIP bit is set when a start bit is detected. The CIP bit is cleared when the final stop bit has been received. SET : Start bit is detected CLEARED : End of word detected SS Synchronous Strip Enable. When this bit is a one, data words that match the synchronous character register will not be loaded into the receive buffer and no buffer full condition will be produced. When this bit is a zero, data words that match the synchronous character register will be transferred to the receive buffer and a buffer full condition will be produced. SET : MPU writes a one 26/42 (R) TS68HC901 CLEARED : MPU writes a zero RE Receiver Enable. When this bit is a zero, the receiver will be immediately disabled. All flags will be cleared. When this bit is a one, normal receiver operation is enabled. This bit should no be set to a one until the receiver clock is active. SET : MPU writes a one or Transmitter is disabled in auto-turnaround mode CLEARED : MPU writes a zero transmitter is disabled, the transmitter will stop at the next rising edge of the internal shift clock. In the asynchronous character format, the transmitter can be programmed to send a break. The break will be transmitted once the word currently in the shift register has been sent. If the shift register is empty, the break command will be effective immediately. An END interrupt will be generated at every normal character boundary to aid in timing the break transmission. The break will continue until the break command is cleared. Any character in the transmit buffer at the start of a break will be transmitted when the break is terminated. If the transmit buffer is empty at the start of a break, it may be written at any time during the break. If the buffer is still empty at the end of the break, an underrun condition will exist. Disabling the transmitter during a break condition causes the transmitter to cease transmission of the break character at the end of the current character. No end of break stop bit will be transmitted. Even if the transmit buffer is empty, no buffer empty condition will occur nor will an underrun condition occur. Also, any word in the transmit buffer will remain. TRANSMITTER INTERRUPT CHANNELS The USART transmit section is assigned two interrrupt channels. One channel indicates a buffer empty condition and the other channel indicates an underrun or end condition. These interrupting conditions correspond to the BE, UE, and END flag bits of the transmitter status register (TSR). The flag bits will function as described below, whether their associated interrupt channel is enabled or disabled. TRANSMITTER STATUS REGISTER The transmitter status register contains various transmitter error flags and transmitter control bits for selecting auto-turnaround and loopback mode. The TSR is shown in Figure 19. DMA OPERATION TRANSMITTER The transmit buffer is loaded by writing to the USART data register (UDR). The data word will be transferred to an internal 8-bit shift register when the last word in the shift register has been transmitted. This will produce a buffer empty condition. If the transmitter completes the transmission of word in the shift register before a new word is written to the transmit buffer, an underrun error will occur. In the asynchronous character format, the transmitter will send a mark until the transmit buffer is written. In the synchronous character format, the transmitter will continuously send the synchronous character. The transmit buffer can be loaded prior to enabling the transmitter. After the transmitter is enabled, there is a delay before the first bit is output. The serial output line (SO) should be programmed to be high, low, or high impedance when the transmitter is enabled to force the output line to the desired state until the first bit is shifted out. Note that a one bit will always be transmitted prior to the word in the transmit shift register when the transmitter is first enabled. When the transmitter is disabled, any word currently being transmitted will continue to completion. However, any word in the transmit buffer will not be transmitted and will remain in the buffer. So, no buffer empty condition will occur. If the buffer is empty when the transmitter is disabled, the buffer empty condition will remain, but no underrun condition will be generated when the word in transmission is completed. If no word is being transmitted when the 27/42 (R) TS68HC901 Figure 19 : 7 0 UE AT END B H L TE TSR (2Dh) BE USART error conditions are only valid for each character boundary. When the USART performs block data transfers by using the DMA handshake line RR (receiver ready) and TR (transmitter ready), errors must be saved and checked at the end of a block. This is accomplished by enabling the error channel for the receiver or transmitter and by masking interrupts for this channel. Once the transfer is complete, interrupt pending register A is read. Any pending receiver or transmitter error indicates an error in the data transfer. BE Buffer Empty. This bit is set when the word in the transmit buffer is transferred to the transmit shift register. This bit is cleared when the transmit buffer is reloaded by writing to the USART data register (UDR). SET : Transmit buffer contents transferred to transmit shift register CLEARED : Transmit buffer written UE Underrun Error. This bit is set when the word in the transmit shift register has been transmitted before a new word is loaded into the transmit buffer. This bit is cleared by reading the TSR or by disabling the transmitter. This bit does not need to be cleared before writing to the UDR. SET : Transmit shift register contents transmitted before transmit buffer written CLEARED : Transmitter status register read or Transmitter disabled AT Auto-Turnaround. When this bit is set, the receiver will be enabled automatically after the transmitter has been disabled and the last character being transmitted is completed. SET : MPU writes a one CLEARED : Transmitter disabled END End of Transmission. When the transmitter is disabled while a character is being transmitted, the END will be set after the character transmission is complete. If no word is being transmitted when the transmitter is disabled, the END bit will be set immediately. The END bit is cleared by reenabling the transmitter. SET : Transmitter disabled CLEARED : Transmitter enabled B H L Output Break. This bit has no function in the 0 0 High Impedance synchronous character format. In the 0 1 LOW asynchronous character format, when 1 0 High this bit is set to a one, a break will be 1 1 Loopback Mode transmitted upon the completion of the transmission of any word in the transmit shift register. A break consists of an all zero data word with no stop bit. When this bit is cleared by software, the break indication will cease and normal transmission will resume. Note that when B is set, BE cannot be set. SET : MPU writes a one CLEARED : MPU writes a zero H, L High and Low. These control bits configure the transmitter output (SO) when the transmitter is disabled. These bits also force the transmitter output after the transmitter is enabled until END is cleared. Loopback mode internally connects the transmitter output to the receiver input and the transmitter clock to the receiver clock internally. The receiver clock (RC) and the serial input (SI) are not used. When the transmitter is disabled, SO is forced high. SET : MPU writes a one 28/42 (R) TS68HC901 TS68HC901 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Symbol VI VDD TA Supply Voltage Operating Temperature Range C suffix Parameter Voltage on Any Pin with Respect to Ground Value - 0.3 to + 7 - 0.3 to + 7 0 to + 70 Unit V V C Tstg Storage Temperature - 65 to + 150 C S tr esses above those listed under "Absolute Maxi mum Rati ngs" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at t hese or any other condit ion above those i ndi cated in the operational sect ions of thi s specifi cation is not implied. Exposure to absolut e maxi mum rating conditi ons f or extended periods may affect reliability. THERMAL CHARACTERISTICS Symbol JA Parameter Thermal Resistance (Plastic) Value 50 Unit C/W D.C. CHARACTERISTICS TA = 0C to 70C ; VCC = + 5V 5% Unless Otherwise Specified Symbol VIH VIH VIL VOH VOL ICC ILI ILOH ILOL IOH IOL Parameter Input High Voltage except XTAL1, XTAL2 Input High Voltage XTAL1, XTAL2 Input Low Voltage Output High Voltage (except DTACK) Output Low Voltage (except DTACK) Power Supply Current Input Leakage Current Tri-state Output Leakage Current in Float Tri-state Output Leakage Current in Float DTACK Output Source Current DTACK Output Sink Current IOH = - 120A IOL = 2.0mA Outputs Open VIN = 0 to VCC VOUT = 2.4 to VCC VOUT = 0.5V VOUT = 2.4 VOUT = 0.5 Test Condition Min. 2.0 - 0.3 4.1 0.5 6 10 10 - 10 - 400 5.3 32 Max. VCC + .3 0.8 Unit V V V V V mA A A A A mA mW VDD-1.5 VCC + .3 Power Dissipation PD A ll voltages are ref erenced to ground. 29/42 (R) TS68HC901 AC ELECTRICAL CHARACTERISTICS (VCC = 5.0Vdc 5%, GND = 0Vdc, TA = 0C to 70C) Number Characteristic 4MHz Min. 1 2 3 4(3) 4a(4) 5 6 7 8 9 10 11(3,5) 12 13 14 15(1) 16 17 18 19(1) 20 21 22 23 24(4) 25 26 27 28 29 Notes : Value 5MHz Min. 35 25 150 50 80 220 60 100 0 50 0 310 50 0 50 180 300 150 180 100 220 250 110 110 100 100 2 450 600 600 1000 200 90 90 80 100 2 450 600 600 50 0 50 180 300 150 165 100 220 1000 125 55 55 50 100 2 350 200 200 0 260 20 0 50 120 180 100 100 100 195 1000 0 50 0 200 180 55 100 0 50 Max. 25 20 100 50 50 90 50 100 8MHz Min. Max. Max. Unit CS, DS Width High R/W, A1-A5 Valid to Falling CS (setup) Data Valid Prior to Falling CLK CS, IACK Valid to Falling Clock (setup) Falling Clock to Next CS Low CLK Low to DTACK Low CS, DS or IACK High to DTACK High CS, DS or IACK High to DTACK Tri-state DTACK Low to Data Invalid (hold time) CS, DS or IACK High to Data Tri-state CS or DS High to R/W, A1-A5 Invalid (hold time) Data Valid from CS Low Read Data Valid to DTACK Low (setup) DTACK Low to DS, CS or IACK High (hold time) IEI Low to Falling CLK (setup) IEO Valid from Clock Low (delay) Data Valid from Clock Low (delay) IEO Invalid from IACK High (delay) DTACK Low from Clock High (delay) IEO Valid from IEI Low (delay) Data Valid from IEI Low (delay) Clock Cycle Time Clock Width Low Clock Width High DS Inactive to rising Clock (setup) I/O Minimum Active Pulse Width IACK Width High I/O Data Valid from Rising CS or DS Receiver Ready Delay from Rising RC Transmitter Ready Delay from Rising TC 1. IEO only goes low if no acknowledgeable interrupt is pending. If IEO goes low, DTACK and the data bus remain tri-stated. 2. TCLK refers to the clock applied to the MFP CLK input pin. tCLK refers to the timer clock signal, regardless of whetherthat signal comes from theXTAL 1/XTAL2 crystal clock inputs or the TAI or TBI timer inputs. 3. If the setup time is not met, CS or IACK will not be recognized until the next falling CLK. 50 30 280 50 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TCLK ns ns ns 4. If this setup time is met (for consecutive cycles), the minimum hold-off time of one clock cycle will be obtained. If not met, the hold-off will be two clock cycles. 5. Although CS and DTACK are synchronized with the clock, the data out during a read cycle is asynchronous to the clock, relying only on CS for timing. 6. Spec. 30 applies to timer outputs TAO and TBO only. 30/42 (R) TS68HC901 AC ELECTRICAL CHARACTERISTICS (continued) (VCC = 5.0Vdc 5%, GND = 0Vdc, TA = 0C to 70C) Number Characteristic 4MHz Min. 30(6) 31(2) 32 33 34 35 36 37 38 Timer Output Low from Rising Edge of CS or DS (A & B) (reset TOUT) TOUT Valid from Internal Timeout Timer Clock Low Time Timer Clock High Time Timer Clock Cycle Time RESET Low Time Delay to Falling INTR from External Interrupt Active Transition Transmitter Internal Interrupt Delay from Falling Edge of TC Receiver Buffer Full Interrupt Transition Delay from Rising Edge of RC Receiver Error Interrupt Transition Delay from Falling Edge of RC Serial in Set Up Time to Rising Edge of RC (divide by one only) Data Hold Time from Rising Edge of RC (divide by one only) Serial Output Data Valid from Falling Edge of TC (/1) Transmitter Clock Low Time Transmitter Clock High Time Transmitter Clock Cycle Time Receiver Clock Low Time Receiver Clock High Time Receiver Clock Cycle Time CS, IACK, DS Width Low Serial Output Data Valid from Falling Edge of TC (/16) 2. TCLK refers to the clock applied to the MFP CLK input pin. tCLK refers to the timer clock signal, regardless of whetherthat signal comes from theXTAL 1/XTAL2 crystal clock inputs or the TAI or TBI timer inputs. 6. Spec. 30 applies to timer outputs TAO and TBO only. Value 5MHz Min. Max. 450 2 tCLK + 300 90 90 1000 380 550 800 200 1.8 380 550 800 1000 55 55 125 1.5 250 350 400 1000 8MHz Min. Max. 200 2 tCLK + 300 Max. 450 2 tCLK + 300 110 110 250 2 Unit ns ns ns ns ns s ns ns ns 39 40 41 800 80 350 70 325 800 50 100 400 ns ns ns 42 43 44 45 46 47 48 49(2) 50 440 500 500 1.05 500 500 1.05 80 490 450 450 0.95 450 450 0.95 420 250 250 0.55 250 250 0.55 80 370 200 ns ns ns s ns ns s 80 250 TCLK ns Notes : 31/42 (R) TS68HC901 TIMER A.C. CHARACTERISTICS Definitions : Error = Indicated Time Value - Actual Time Value tpsc = t CLKx Prescale Value Internal Timer Mode Single Interval Error (free running) (note 2) Cumulative Internal Error Error between Two Timer Reads Start Timer to Stop Timer Error Start Timer to Read Timer Error Start Timer to Interrupt Request Error (note 3) 100ns 0 (tpsc + 4tCLK) + (2t CLK + 100ns) to - (tpsc + 6tCLK + 100ns) + 0 to - (tpsc + 6tCLK + 400ns) - 2tCLK to - (4tCLK + 800ns) PULSE WIDTH MEASUREMENT MODE Measurement Accuracy (note 1) Minimum Pulse Width + 2tCLK to - (tpsc + 4tCLK) 4t CLK EVENT COUNTER MODE Minimum Active Time of TAI, TBI Minimum Inactive Time of TAI, TBI Notes : 1.Error may be cumulative if repetitively performed. 2.Error with respect to TOUT or INT if note 3 is true. 3.Assuming it is possible for the timer to make an interrupt request immediately. 4t CLK 4t CLK 32/42 (R) TS68HC901 Figure 21 : Figure 22 : No te : CS and IACK must be a f unction of DS. 33/42 (R) TS68HC901 Figure 23 : Figure 24 : Note : CS and IACK must be a function of DS. 34/42 (R) TS68HC901 Figure 25 : Interrupt Timing Figure 26 : Port Timing Note : Active edge i s assumed to be t he rising edge. 35/42 (R) TS68HC901 Figure 27 : Receiver Timing Figure 28 : Transmitter Timing 36/42 (R) TS68HC901 Figure 29 : Timer Timing Figure 30 : Reset Timing 37/42 (R) TS68HC901 AC ELECTRICAL CHARACTERISTICS - MULTIPLEXED BUS TIMING (VCC=5.0V VDC5%, VSS=0VDC, TA=0 to 70C unless otherwise noted) See fiN 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Cycle Time Pulse Width DS Low or RD/WR High Pulse Width DS High or RD/WR Low Pulse Width AS/ALE High Delay AS Fall to DS Rise or ALE Fall to RD/WR Fall Delay DS or RD/WR Rise to AS/ALE Rise R/W Setup Time to DS R/W Hold Time to DS Address Setup Time to AS/ALE Address Hold Time to AS/ALE Data Setup Time to DS or WR (Write) Delay Data to DS or RD (Read) Data Hold Time to DS or WR (Write) Data Hold Time to DS or RD (Read) CE Setup Time to AS/ALE Fall CE Hold Time to DS, RD or WR 20 0 20 20 100 Parameter Min. 800 350 340 100 30 30 100 10 20 20 280 250 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 31 : Multiplexed Bus Timing Motorola Type 38/42 (R) TS68HC901 Figure 32 : Multiplexed Bus Timing - Intel Type 39/42 (R) TS68HC901 Figure 33 : Typical Test Load Figure 34 : INTR Test Load F or all outputs except DTACK C L = 100pf R L = 20k R 1 = 1. 9k For DTACK C L = 130pf R L = 6k R 1 = 740 CAPACITANCE T A = 25C, f = 1MHz unmeasured pins returned to ground. Symbol C IN C OUT Parameter Input Capacitance Tri-state Output Capacitance Test Condition Unmeasured pins returned to ground Max. 10 10 Unit pF pF Figure 35 : External Oscillator Components Figure 36 : External Clock Connection. CRYSTAL PARAMET ERS : Parallel resonance, f undament al mode AT cut R S 150 (F R = 2.8 - 5.0MHz); R S 300 (F R = 2.0 - 2.7MHz) C L = 18pf ; CM = 0.02pf ; Ch = 5pf ; LM = 96mH F R (typ) = 2.4576MHz OT HER POSSIBLE CONFIGURATION: XTA L1 dri ven with a CMOS clock and XTAL2 not connect ed CLOCK TIMING Value Symbol f tcyc tCL, tCH tCr, tCf 40/42 (R) Parameter Frequency of Operation Cycle Time Clock Pulse Width Rise and Fall Times 4MHz Min. 1.0 250 110 Max. 4.0 1000 480 15 5MHz Min. 1.0 200 90 Max. 5.0 1000 480 10 8MHz Min. 1.0 125 55 Max. 8.0 1000 480 10 Unit MHz ns ns ns TS68HC901 48 PIN PLASTIC DUAL-IN-LINE PACKAGE, 600 MIL WIDTH (P) Dim. A A1 B B1 C D D1 E E1 K1 K2 L e1 N mm inches Min Typ Max Min Typ 2.2 4.8 0.086 0.51 1.77 0.010 0.38 0.58 0.015 0.97 1.52 0.055 0.2 0.3 0.008 60.46 61.62 2.400 - - - - - 16.3 12.9 0.508 - - - - - - - - - - 3.18 4.44 1.25 2.54 0.10 Number of Pins 48 Max 0.189 0.069 0.023 0.065 0.009 2.425 - 0.641 - - 0.174 52 PIN PLASTIC LEADLESS CHIP CARRIER PACKAGE (FN) Dim. A A1 A3 B B1 D D1 D3 E E1 E3 K1 e N ND NE mm inches Min Typ Max Min Typ 4.20 5.08 0.165 0.64 0.025 2.29 3.30 0.090 0.331 0.533 0.013 0.661 0.812 0.026 19.94 20.19 0.785 19.050 19.202 0.750 15.24 0.600 19.94 20.19 0.785 19.050 19.202 0.750 15.24 0.600 1.27 0.050 Number of Pins 52 13 13 Max 0.200 0.130 0.021 0.032 0.795 0.756 0.795 0.756 - 41/42 (R) TS68HC901 TS68HC901 ORDERING INFORMATION Part Number TS68HC901CP4 TS68HC901CP5 TS68HC901CP8 TS68HC901CFN4 TS68HC901CFN5 TS68HC901CFN8 Package Type Plastic DIP Max. Clock Frequency 4.0MHz 5.0MHz 8.0MHz 4.0MHz 5.0MHz 8.0MHz Temperature Range 0 to 70C PLCC 0 to 70C Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All rights reserved. Purchase of I2C Components by SGS-THOMSON Microelectronics conveys a license under the Philips I 2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I 2C Standard Specification as defined by Philips. SGS-THOMSON Microelectronics Group of Companies Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 42/42 (R) |
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